The present invention relates to an interface controller, and more particularly, to an interface controller which conforms to the IEEE 1394 Standard.
FIG. 1 is a system block diagram in which a personal computer (PC) 30, a digital video camera (DVC) 31 and a video cassette recorder (VCR) 32 are connected by an IEEE 1394 bus 33. Each of the PC 30, DVC 31 and VCR 32 is provided with a repeat function which mediates a data transfer.
FIG. 2 is a schematic diagram of a conventional interface controller 35 of the DVC 31. The interface controller 35 includes input/output ports 36 and 37, interface circuits 38 and 39, a buffer 40 and a clock generator 41.
When the DVC 31 receives data addressed to it, the data is temporally stored in the buffer 40 from the input/output ports 36 and 37 via the interface circuits 38 and 39. The data is provided from the buffer 40 to an internal processing circuit (not shown) which performs image processing. When the DVC 31 outputs image data, the image data from the internal processing circuit is temporally stored in the buffer 40 and the image data is provided from the buffer 40 to the input/output ports 36, 37 via the interface circuits 38 and 39. In this manner, the data transfer between the PC 30 and the DVC 31 or between the DVC 31 and the VCR 32 is performed.
Further, when the DVC 31 receives data not addressed to it, that is, when data transfer is performed between the PC 30 and the VCR 32, the interface controller 35 of the DVC 31 mediates the data transfer. In other words, the interface controller 35 executes a repeat transfer.
Specifically, the data passed between the PC 30 and VCR 32 is temporally stored in the buffer 40 via the input/output ports 36 and 37 and the interface circuits 38 and 39. Then, the data transfer between the PC 30 and the VCR 32 is performed by clocking the interface circuits 38, 39 using a clock signal of the clock generator 41. In FIG. 2, the single-dot chain lines indicate the flow of data from the VCR 32 to the PC 30 and the two-dot chain lines indicate the flow of data from the PC 30 to the VCR 32.
The IEEE 1394 Standard defines transfer rates (or the communication performance) of 100 megabits per second, 200megabits per second and 400 megabits per second. Accordingly, at the time of designing a device, an appropriate data rate is selected based on the data transfer requirement of the device and the power consumption requirement. In other words, a device, such as a portable device powered by a battery, is set to a low transfer rate to reduce the power consumption. For example, the DVC 31, since it is usually battery powered, is normally set to the transfer rate of 100 megabits per second. On the one hand, the PC 30 and the VCR 32, which are powered by an external household power supply, are set to the transfer rate of 400 megabits per second.
However, when the repeat transfer is conducted, the transfer rate is determined depending on the clock frequency of the clock generator of the mediating device. As shown in FIG. 3, when the DVC 31 having low-speed communication performance is connected between the PC 30 and the VCR 32 which have high-speed communication performance, the repeat transfer operation is performed at the low-speed transfer rate of 100 megabits per second. As a result, the performance of the PC 30 and/or VCR 32 is not used efficiently. Further, if the DVC 31, as a portable device, is designed for high speed, its power consumption increases. Accordingly, when the DVC 31 is powered by a battery, such high power consumption will cause problems.
If the PC 30 and the VCR 32 are connected in the relationship of xe2x80x9cPC 30 to VCR 32 to DVC 31xe2x80x9d as shown in FIG. 4, communication can be performed between the two devices 30 and 32 at 400 megabits per second. However, to connect the devices this manner, the communication speed of each device must be considered. In particular, if the device is used in a home, it is difficult to insure such connection.
It is an object of the present invention to provide an interface controller which provides the optimum communication performance.
In one aspect of the present invention, an interface controller connected to a plurality of devices is provided. The interface controller includes a clock generating unit for generating a clock signal having a frequency. A transfer unit performs one of a first data transfer and a second data transfer in accordance with the clock signal. The first data transfer is performed between a first other device and a second other device via the transfer unit and a second data transfer is performed between the transfer unit and one of the other devices. A clock control unit adaptively changes the frequency of the clock signal between the first and second data transfers.
In another aspect of the present invention, an interface controller for setting a data transfer rate of data transferred between at least two devices connected to a bus is provided. The interface controller includes an I/O port connected to the bus for sending and receiving data. An interface circuit passes data to and from the I/O port at a data transfer rate determined by a clock signal. A buffer circuit stores the data received from the I/O port and for storing internally generated data. A clock signal generator generates the clock signal. A control circuit generates a control signal used to change the frequency of the clock signal provided to the interface circuit.
In another aspect of the present invention, a method for transferring data between a self device and a plurality of other devices is provided. First, it is determined whether the data to be transferred is addressed to the self device or to one of the other devices. Then, a first data transfer is performed between a first other device and a second other device via the self device at a first transfer rate when the data is addressed to one of the other devices. A second data transfer is performed between the self device and one of the other devices at a second transfer rate that is slower than the first transfer rate when the data is addressed to the self device.
In yet another aspect of the present invention, a method for transferring data between a self device and a plurality of other devices is provided. The self device is powered by one of an internal power supply and an external power supply. First, it is determined whether the data to be transferred is addressed to the self device or to one of the other devices. Then, a first data transfer is performed between a first other device and a second other device via the self device at a first transfer rate when the data is addressed to one of the other devices and the self device is powered by the external power supply. A second data transfer is performed between the self device and one of the other devices at a second transfer rate that is slower than the first transfer rate when the data is addressed to the self device and the self device is powered by the internal power supply.